

& Xilinx Virtex FPGA Front End Processor Cards
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3U VPX Single or Dual Core Freescale Single Board Computer
Model TIC-PPC-VPX3a
Ruggedize your SBC or bundle it in a fully integrated package including mezzanine options and OS integration sold and supported under a single assembly number.
The TIC-PPC-VPX3a is compliant with the following OpenVPX profiles (VITA 65) :
• MOD3-PAY-2F2U-16.2.3-2
• MOD3-PAY-2F2T-16.2.5-2
• MOD3-PAY-1D-16.2.6-1
• MOD3-PAY-2F-16.2.7-1

3U VPX Low Power Freescale MPC8536E based Single Board Computer
Model TIC-PQ3-VPX3a
Ruggedize your SBC or bundle it in a fully integrated package including mezzanine options and OS integration sold and supported under a single assembly number.
The TIC-PQ3-VPX3a is compliant with the following OpenVPX profiles (VITA 65) :
Features
I/0 Subsystem
Xilinx Virtex-6 FPGA Front End Processing Board
Model TIC-FEP-VPX3b
For compute intensive applications including radar signal
processing, image processing and others requiring high bandwidth signal
pre-processing and data communications.
The TIC-FEP-VPX3b provides one VITA 57 FMC site for reconfigurable I/O capability.
Processing Unit
• Xilinx Virtex-6 XC6VSX315T (or XC6VLX195T)
• Two banks of DDR3-800: 40-bit wide, 1.25 GBytes each
• Optional pipelined NoBlocking SRAM: 18-bit wide / 9 MBytes flash
•One NOR flash eeprom (128 MBytes)
• One SPI flash (16 MBytes)
• Spartan®-6 LX-25T (control Node)
VPX Interfaces
• Four 4-lane Fabric ports (on P1)
• Four GTX x4 channel (Fat Pipes A, B, C & D)
(one lane of Fat Pipe D can be used to feed the Spartan-6)
• General purpose IOs (on P2)
• Sixteen differential pairs (from FPGA)
• Sixteen differential pairs (from FMC IOs connector)
• GPIOs user-defined on P1
FMC Connector
• One GTPx4 link
• 68 differential pairs
• Four clocks (LVDS Diff)
Current Elma FMC modules:
• TIC-DAC-FMCa: Quad 16-bit 800 Msps DAC
• TIC-ADC-FMCa: Quad 16-bit 135/200 Msps ADC
• TIC-ADC-FMCb: Quad 14-bit 250 Msps ADC
Xilinx Virtex-6 FPGA Front End Processing Board
Model TIC-FEP-VPX6a
For compute intensive applications including radar signal
processing, image processing and others requiring high bandwidth signal
pre-processing and data communications.
The TIC-FEP-VPX6a is a VPX hybrid processing engine combining the latest generation of FPGAs and processors to deliver high performance levels per watt.
Processing Units
One QorIQ processor P2020, 1GHz, e500 v2 core with :
o 1 GB of DDR3 with ECC
o 256 or 512 MBytes of NOR Flash
o Optional NAND Solid-state Disk (eUSB module)
Two Xilinx Virtex-6 : SX315T (-1 or -2) or SX475T (-1 only) or LX550T,
both offering:
o Two banks of DDR3 : 40-bit wide, 1.25 GBytes each
o One SRAM DDRII : 18-bit wide / 9 MB
o One SPI flash (16 MBytes)
One Spartan®-6 LX-45T (control Node)
o One NOR flash (128 MBytes, for bit streams
VPX Interfaces
Four PCIe x4 port (from PCIe switch)
GTX ports (1 or 2 * GTX x8 from each FPGAs)
Two GTP (from Ctrl node FPGA)
General purpose I/Os
o Two 16LVDS (16 from each FPGAs)
o Two 16 differential pairs (16 from each FMC I/O connector)
GPIOs (from ctrl node FPGA)
Two Ethernet ports (1000BT or 1000BX - from P2020)
One RS485/RS232 port
Two USB 2.0 ports
PIC μ-controller for System Management (per VITA 46.11)
FMC Interfaces
80 LVDS
Four reference clocks
One GTX x4 link
Current Elma FMC modules:
• TIC-DAC-FMCa: Quad 16-bit 800 Msps DAC
• TIC-ADC-FMCa: Quad 16-bit 135/200 Msps ADC
• TIC-ADC-FMCb: Quad 14-bit 250 Msps ADC